Instruction set architecture

Instruction set architecture

In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation. In general, an ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA.

Comment
enIn computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation. In general, an ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA.
Date
enDecember 2021
Depiction
Mips32 addi.svg
DifferentFrom
Industry Standard Architecture
Has abstract
enIn computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as a central processing unit (CPU), is called an implementation. In general, an ISA defines the supported instructions, data types, registers, the hardware support for managing main memory, fundamental features (such as the memory consistency, addressing modes, virtual memory), and the input/output model of a family of implementations of the ISA. An ISA specifies the behavior of machine code running on implementations of that ISA in a fashion that does not depend on the characteristics of that implementation, providing binary compatibility between implementations. This enables multiple implementations of an ISA that differ in characteristics such as performance, physical size, and monetary cost (among other things), but that are capable of running the same machine code, so that a lower-performance, lower-cost machine can be replaced with a higher-cost, higher-performance machine without having to replace software. It also enables the evolution of the microarchitectures of the implementations of that ISA, so that a newer, higher-performance implementation of an ISA can run software that runs on previous generations of implementations. If an operating system maintains a standard and compatible application binary interface (ABI) for a particular ISA, machine code will run on future implementations of that ISA and operating system. However, if an ISA supports running multiple operating systems, it does not guarantee that machine code for one operating system will run on another operating system, unless the first operating system supports running machine code built for the other operating system. An ISA can be extended by adding instructions or other capabilities, or adding support for larger addresses and data values; an implementation of the extended ISA will still be able to execute machine code for versions of the ISA without those extensions. Machine code using those extensions will only run on implementations that support those extensions. The binary compatibility that they provide makes ISAs one of the most fundamental abstractions in computing.
Is primary topic of
Instruction set architecture
Label
enInstruction set architecture
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0-operand instruction set
360
3DNow!
Abstract model
Accumulator (computing)
Accumulator machine
Addressing mode
Advanced Micro Devices
AltiVec
Application binary interface
Architecture
Arithmetic logic unit
Arity
ARM architecture
ARM Thumb
ARMv7
Assembly language
Athlon
Atomic instruction
AVR32
Binary compatibility
Binary multiplier
Bitwise operation
Branch (computer science)
Branch predication
Byte
Bytecode
Call stack
Category:Central processing unit
Category:Instruction processing
Category:Instruction set architectures
Category:Microprocessors
Central processing unit
Cjip
Common Language Runtime
Compare-and-swap
Comparison of instruction set architectures
Compiler
Complex instruction set computer
Compressed instruction set
Computer
Computer architecture
Computer performance
Computer science
Computing
Control flow
Control unit
Cosine
CPU cache
Data type
DEC Alpha
Delay slot
Digital signal processor
DMA transfer
Emulator
Executable compression
Explicitly parallel instruction computing
Fetch-and-add
Field-programmable gate array
File:Mips32 addi.svg
Flag (computing)
Flash memory
Floating-point arithmetic
Fred Brooks
Halfword
Harvard architecture
High-level programming language
Imsys
Indirect branch
Instruction-level parallelism
Instruction pipeline
Instruction set simulator
Intel
Interpreter (computing)
Java virtual machine
Just-in-time compilation
Kolmogorov complexity
Load and store
Load–store architecture
Logarithm
Logical conjunction
Logical disjunction
Logical negation
Machine code
Mainframe computer
MCP-1600
Memory consistency
Microarchitecture
Microcode
Microcontroller
Micro-operation
Microsoft
Minimal instruction set computer
MIPS architecture
MMX (instruction set)
MOS Technology 6502
Motorola 68000
Multi-core
Multiply–accumulate
Non-blocking synchronization
NOP (code)
NOP slide
One-instruction set computer
Opcode
Operand
Operating system
output
OVPsim
P5 (microarchitecture)
Parallelization
Personal computer
Popek and Goldberg virtualization requirements
Power ISA
Processor design
Processor register
Programmable logic array
Programming model
RAM
Random-access memory
Read-modify-write
Read-only memory
Reconfigurable computing
Reduced instruction set computer
Register (computer)
Register spilling
Register transfer language
Rekursiv
Reverse Polish notation
SIMD register
Simulation
Sine
Single instruction, multiple data
Smalltalk
Software interrupt
SPARC
Square root
Stack (abstract data type)
Stack (data structure)
Stack machine
Status register
store-conditional
String copy
Subroutine
Supercomputer
System call
Test-and-set
TI MSP430
Transcendental function
Transmeta
Transport triggered architecture
Typified
Variable-length code
VAX
Vector processing
Very long instruction word
Virtual machine
Virtual memory
VLIW
Western Digital
Word (data type)
Writable control store
X86 instruction set
Zilog Z80
Reason
enThat discusses RISC and CISC, but not MISC.
SameAs
2YYZF
4129931-0
Architektura zestawu instrukcji
Arhitektura seta instrukcija
Befehlssatzarchitektur
Conjunt d'instruccions
Conjunto de instrucciones
Conjunto de instruções
Instructieset
Instruction set
Instruction set
Instruction Set Architecture
Instrukciju kopa
Instrukční sada
Inštrukčný súbor
Instruksjonssett
Instruktionssæt
Instruktionsuppsättning
Jeu d'instructions
Käsustik
Kiến trúc tập lệnh
Komut kümesi
Q272683
Set de instrucțiuni
Set instruksi
Skup naredbi
Tacar treoracha
Utasításkészlet
Αρχιτεκτονική συνόλου εντολών
Архитектура набора команд
Архітектура системи команд
Командын багц
Набор от инструкции
Наредбено множество
Скуп инструкција
סט פקודות
مجموعة التعليمات
مجموعه دستورالعمل
کۆمەڵە فەرمان
ہدایتی طاقم
ഇൻസ്ട്രക്ഷൻ സെറ്റ് ആർക്കിടെക്ചർ
ชุดของคำสั่งเครื่อง
命令セット
指令集架構
명령어 집합
Subject
Category:Central processing unit
Category:Instruction processing
Category:Instruction set architectures
Category:Microprocessors
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47772
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WikiPageUsesTemplate
Template:Anchor
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Template:CPU technologies
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Template:Machine code
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