Load–store architecture
In computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach.
- Comment
- enIn computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach.
- Date
- enJune 2020
- Has abstract
- enIn computer engineering, a load–store architecture is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers). Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures. For instance, in a load–store approach both operands and destination for an ADD operation must be in registers. This differs from a register-memory architecture (for example, a CISC instruction set architecture such as x86) in which one of the operands for the ADD operation may be in memory, while the other is in a register. The earliest example of a load–store architecture was the CDC 6600. Almost all vector processors (including many GPUs) use the load–store approach.
- Is primary topic of
- Load–store architecture
- Label
- enLoad–store architecture
- Link from a Wikipage to another Wikipage
- Arithmetic logic unit
- ARM architecture
- Category:Computer architecture
- CDC 6600
- Complex instruction set computing
- Computer engineering
- GPUs
- Instruction set architecture
- Load and store
- Load–store unit
- Memory (computing)
- MIPS architecture
- PowerPC
- Processor register
- Reduced instruction set computing
- Register-memory architecture
- Register–memory architecture
- RISC-V
- SPARC
- Vector processor
- X86
- Reason
- enIn need of a better source to explain how 'many' GPUs use load–store than a datasheet on a particular architecture.
- SameAs
- 4r1Kh
- Arquitectura de carga-almacenamiento
- Arsitektur muat dan simpan
- Q6663274
- store
- store (processadors)
- Store-Architektur
- Архітектура load-store
- 載入-儲存架構
- Subject
- Category:Computer architecture
- WasDerivedFrom
- Load–store architecture?oldid=1114083842&ns=0
- WikiPageLength
- 2115
- Wikipage page ID
- 35161236
- Wikipage revision ID
- 1114083842
- WikiPageUsesTemplate
- Template:Better source
- Template:Comp-eng-stub
- Template:Reflist
- Template:Rp
- Template:Short description