Transport triggered architecture
In computer architecture, a transport triggered architecture (TTA) is a kind of processor design in which programs directly control the internal transport buses of a processor. Computation happens as a side effect of data transports: writing data into a triggering port of a functional unit triggers the functional unit to start a computation. This is similar to what happens in a systolic array. Due to its modular structure, TTA is an ideal processor template for application-specific instruction set processors (ASIP) with customized datapath but without the inflexibility and design cost of fixed function hardware accelerators.
- Comment
- enIn computer architecture, a transport triggered architecture (TTA) is a kind of processor design in which programs directly control the internal transport buses of a processor. Computation happens as a side effect of data transports: writing data into a triggering port of a functional unit triggers the functional unit to start a computation. This is similar to what happens in a systolic array. Due to its modular structure, TTA is an ideal processor template for application-specific instruction set processors (ASIP) with customized datapath but without the inflexibility and design cost of fixed function hardware accelerators.
- Date
- 3 March 2016
- Depiction
- Has abstract
- enIn computer architecture, a transport triggered architecture (TTA) is a kind of processor design in which programs directly control the internal transport buses of a processor. Computation happens as a side effect of data transports: writing data into a triggering port of a functional unit triggers the functional unit to start a computation. This is similar to what happens in a systolic array. Due to its modular structure, TTA is an ideal processor template for application-specific instruction set processors (ASIP) with customized datapath but without the inflexibility and design cost of fixed function hardware accelerators. Typically a transport triggered processor has multiple transport buses and multiple functional units connected to the buses, which provides opportunities for instruction level parallelism. The parallelism is statically defined by the programmer. In this respect (and obviously due to the large instruction word width), the TTA architecture resembles the very long instruction word (VLIW) architecture. A TTA instruction word is composed of multiple slots, one slot per bus, and each slot determines the data transport that takes place on the corresponding bus. The fine-grained control allows some optimizations that are not possible in a conventional processor. For example, software can transfer data directly between functional units without using registers. Transport triggering exposes some microarchitectural details that are normally hidden from programmers. This greatly simplifies the control logic of a processor, because many decisions normally done at run time are fixed at compile time. However, it also means that a binary compiled for one TTA processor will not run on another one without recompilation if there is even a small difference in the architecture between the two. The binary incompatibility problem, in addition to the complexity of implementing a full context switch, makes TTAs more suitable for embedded systems than for general purpose computing. Of all the one-instruction set computer architectures, the TTA architecture is one of the few that has had processors based on it built, and the only one that has processors based on it sold commercially.
- Hypernym
- Kind
- Is primary topic of
- Transport triggered architecture
- Label
- enTransport triggered architecture
- Link from a Wikipage to an external page
- www.drdobbs.com/embedded-systems/221800122
- sites.google.com/site/macthenaief/Home/retro/able
- web.archive.org/web/20071013182106/http:/byte.com/art/9502/sec13/art1.htm
- web.archive.org/web/20120210164833/http:/ce.et.tudelft.nl/MOVE/
- web.archive.org/web/20120210164833/http:/ce.et.tudelft.nl/MOVE/section3.3.html
- www.ics.ele.tue.nl/~heco/documents/TTAbook/TTAbook.html
- web.archive.org/web/20160303174923/http:/www.ics.ele.tue.nl/~heco/documents/TTAbook/TTAbook.html
- www.quinapalus.com/wi-index.html
- Link from a Wikipage to another Wikipage
- Abstraction (computer science)
- Accumulator (computing)
- Addressing mode
- Application-specific instruction set processor
- Application-specific instruction-set processor
- Bus (computing)
- Category:Computer architecture
- Category:Instruction processing
- Clock cycle
- Compile time
- Computer architecture
- Computer bus
- Computer memory
- Conditional execution
- Conditional register
- Control flow
- CPU power dissipation
- Dataflow architecture
- Delay slot
- Embedded system
- Explicitly parallel instruction computing
- File:Transport Triggered Architecture.png
- For-loop
- Functional unit
- General purpose register
- If-then-else
- Instruction level parallelism
- Instruction pipeline
- Interconnect architecture
- Load–store unit (computing)
- Macro instruction
- Mali (GPU)
- Maxim Integrated
- Microarchitectural
- New England Digital
- One-instruction set computer
- OpenASIP
- Operator (programming)
- Original Amiga chipset
- Pipeline (computing)
- Processor (computing)
- Program counter
- Register file
- Register pressure
- Run time (program lifecycle phase)
- Subroutine
- Systolic array
- Very long instruction word
- WireWorld
- SameAs
- 2CXeq
- m.085gt5
- Q2329233
- Transport triggered architecture
- Transport triggered architecture
- Transport triggered architecture
- Transport triggered architecture
- Subject
- Category:Computer architecture
- Category:Instruction processing
- Thumbnail
- Url
- TTAbook.html
- WasDerivedFrom
- Transport triggered architecture?oldid=1119680420&ns=0
- WikiPageLength
- 17914
- Wikipage page ID
- 2830935
- Wikipage revision ID
- 1119680420
- WikiPageUsesTemplate
- Template:Citation needed
- Template:CPU technologies
- Template:Main article
- Template:Short description
- Template:Webarchive
