Explicit data graph execution
Explicit data graph execution, or EDGE, is a type of instruction set architecture (ISA) which intends to improve computing performance compared to common processors like the Intel x86 line. EDGE combines many individual instructions into a larger group known as a "hyperblock". Hyperblocks are designed to be able to easily run in parallel.
- Comment
- enExplicit data graph execution, or EDGE, is a type of instruction set architecture (ISA) which intends to improve computing performance compared to common processors like the Intel x86 line. EDGE combines many individual instructions into a larger group known as a "hyperblock". Hyperblocks are designed to be able to easily run in parallel.
- Has abstract
- enExplicit data graph execution, or EDGE, is a type of instruction set architecture (ISA) which intends to improve computing performance compared to common processors like the Intel x86 line. EDGE combines many individual instructions into a larger group known as a "hyperblock". Hyperblocks are designed to be able to easily run in parallel. Parallelism of modern CPU designs generally starts to plateau at about eight internal units and from one to four "cores", EDGE designs intend to support hundreds of internal units and offer processing speeds hundreds of times greater than existing designs. Major development of the EDGE concept had been led by the University of Texas at Austin under DARPA's Polymorphous Computing Architectures program, with the stated goal of producing a single-chip CPU design with 1 TFLOPS performance by 2012, which has yet to be realized as of 2018.
- Hypernym
- Instruction
- Is primary topic of
- Explicit data graph execution
- Label
- enExplicit data graph execution
- Link from a Wikipage to an external page
- www.cs.utexas.edu/users/cart/trips/publications/cgo06.pdf
- www.cs.utexas.edu/~trips/overview.html
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- 360
- Arithmetic logic unit
- Basic block
- C++
- Carnegie Mellon University
- Category:Instruction set architectures
- Compiler
- Complex instruction set computing
- DARPA
- Data-flow analysis
- Dataflow language
- Floating point unit
- High level language
- IBM
- IBM 801
- Instruction set architecture
- Intel x86
- Intermediate code
- Itanium
- Main memory
- Microcode
- Motorola 68000
- Processor register
- Prograph
- Reduced instruction set computing
- Single instruction, multiple data
- Source code
- Subroutines
- Superscalar
- Telephone switch
- University of Texas at Austin
- University of Washington
- Very long instruction word
- SameAs
- 3T3re
- Explicit data graph execution
- Explicit Data Graph Execution
- Explicit Data Graph Execution
- Explicit Data Graph Execution
- Explicit Data Graph Execution
- m.02qt4vx
- Q3736059
- Subject
- Category:Instruction set architectures
- WasDerivedFrom
- Explicit data graph execution?oldid=1091374498&ns=0
- WikiPageLength
- 17594
- Wikipage page ID
- 10890306
- Wikipage revision ID
- 1091374498
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- Template:CPU technologies
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