Program status word
The program status word (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360 and its successors, and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit. Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.
- Comment
- enThe program status word (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360 and its successors, and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit. Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions.
- Has abstract
- enThe program status word (PSW) is a register that performs the function of a status register and program counter, and sometimes more. The term is also applied to a copy of the PSW in storage. This article only discusses the PSW in the IBM System/360 and its successors, and follows the IBM convention of numbering bits starting with 0 as the leftmost (most significant) bit. Although certain fields within the PSW may be tested or set by using non-privileged instructions, testing or setting the remaining fields may only be accomplished by using privileged instructions. Contained within the PSW are the two bit condition code, representing zero, positive, negative, overflow, and similar flags of other architectures' status registers. Conditional branch instructions test this encoded as a four bit value, with each bit representing a test of one of the four condition code values, 23 + 22 + 21 + 20. (Since IBM uses big-endian bit numbering, mask value 8 selects code 0, mask value 4 selects code 1, mask value 2 selects code 2, and mask value 1 selects code 3.) The 64-bit PSW describes (among other things) * Interrupt masks * Privilege states * Condition code * Instruction address In the early instances of the architecture (System/360 and early System/370), the instruction address was 24 bits; in later instances (XA/370), the instruction address was 31 bits plus a mode bit (24 bit addressing mode if zero; 31 bit addressing mode if one) for a total of 32 bits. In the present instances of the architecture (z/Architecture), the instruction address is 64 bits and the PSW itself is 128 bits. The PSW may be loaded by the LOAD PSW instruction (LPSW or LPSWE). Its contents may be examined with the Extract PSW instruction (EPSW).
- Hypernym
- Architecture
- Is primary topic of
- Program status word
- Label
- enProgram status word
- Link from a Wikipage to an external page
- bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf
- bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf%23page=16
- bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf%23page=177
- bitsavers.org/pdf/ibm/360/princOps/A22-6821-7_360PrincOpsDec67.pdf%23page15
- publibfp.boulder.ibm.com/epubs/pdf/a227832c.pdf
- publibfp.boulder.ibm.com/epubs/pdf/a227832c.pdf%23p=202
- publibfp.boulder.ibm.com/epubs/pdf/a227832c.pdf%23page=199
- publibz.boulder.ibm.com/epubs/pdf/dz9ar008.pdf%23page=115
- bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf
- bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf%23page=154
- bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf%23page=158
- bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf%23page=79
- bitsavers.org/pdf/ibm/370/princOps/GA22-7000-10_370_Principles_of_Operation_Sep87.pdf%23page=81
- bitsavers.org/pdf/ibm/360/functional_characteristics/GA27-2719-2_360-67_funcChar.pdf
- bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf%23page=15
- bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf%23page=16
- bitsavers.org/pdf/ibm/360/funcChar/GA27-2719-2_360-67_funcChar.pdf%23page=57
- bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf
- bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf%23page=76
- bitsavers.org/pdf/ibm/370/princOps/SA22-7200-0_370-ESA_Principles_of_Operation_Aug88.pdf
- bitsavers.org/pdf/ibm/370/princOps/SA22-7200-0_370-ESA_Principles_of_Operation_Aug88.pdf%23page=82
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- 32-bit
- 360
- 360 mainframe line
- 360 Model 67
- Architecture
- Branch (computer science)
- Category:Central processing unit
- Category:Control flow
- Category:Digital registers
- Condition code register
- Interrupt mask
- Load Program Status Word instruction
- Program counter
- Status register
- SameAs
- 53yqF
- m.09448
- Programstatusord
- Program status word
- Program status word
- Program Status Word
- Program Status Word
- Q9063099
- کلمه وضعیت برنامه
- 程序状态字
- Subject
- 360 mainframe line
- Category:Central processing unit
- Category:Control flow
- Category:Digital registers
- WasDerivedFrom
- Program status word?oldid=1088832842&ns=0
- WikiPageLength
- 77492
- Wikipage page ID
- 3299290
- Wikipage revision ID
- 1088832842
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